Generally, USB devices, PCIe devices, mobile industry processor interface (MIPI) devices transmit data according to differential signals. In addition, these devices are usually equipped with squelch detectors to detect whether the differential signals are valid.
FIG. 1A schematically illustrates the relationships between associated signals and a squelch detector. FIG. 1B is a schematic timing waveform diagram illustrating associated signals processed by the squelch detector. The squelch detector 10 receives a first input signal VP and a second input signal VM. The first input signal VP and the second input signal VM are collaboratively defined as a differential input signal. Moreover, the squelch detector 10 receives a first reference voltage VREFP and a second reference voltage VREFN, wherein the first reference voltage VREFP is higher than the second reference voltage VREFN. Moreover, the difference between the first reference voltage VREFP and the second reference voltage VREFN is defined as a squelch threshold.
Generally, the squelch detector 10 judges the differential input signal according to the squelch threshold, and generating a detected signal Sout according to the judging result. The detected signal Sout indicates whether the differential input signal is valid or not.
Please refer to FIG. 1B. Before the time point t1, the differential input signal is in an idle state. Consequently, the differential input signal is maintained at the same voltage. The magnitude of this voltage is in the range between the first reference voltage VREFP and the second reference voltage VREFN. Under this circumstance, the detected signal Sout is in a first logic-level state (e.g. a high logic-level state). The detected signal Sout in the first logic-level state represents the invalid differential input signal. The invalid differential input signal is also referred as a squelched signal.
In the time interval between the time point t1 and the time point t2, the maximum values of the first input signal VP and the second input signal VM are higher than the first reference voltage VREFP, and the minimum values of the first input signal VP and the second input signal VM are lower than the second reference voltage VREFN. Under this circumstance, the detected signal Sout is in a second logic-level state (e.g. a low logic-level state). The detected signal Sout in the second logic-level state represents the valid differential input signal. The valid differential input signal is also referred as a not-squelched signal.
After the time point t2, the maximum values of the first input signal VP and the second input signal VM are lower than the first reference voltage VREFP, and the minimum values of the first input signal VP and the second input signal VM are higher than the second reference voltage VREFN. Under this circumstance, the detected signal Sout is in the first logic-level state (e.g. the high logic-level state). The detected signal Sout in the first logic-level state represents the invalid differential input signal or the squelched signal.
Generally, if the detected signal Sout represents the invalid differential input signal, it means that the first input signal VP and the second input signal VM are bad signals or noise.
FIG. 2 schematically illustrates the architecture of a conventional squelch detection system for high speed data links. This squelch detection system is disclosed in U.S. Pat. No. 7,471,118 for example. As shown in FIG. 2, the squelch detection system 100 comprises plural difference blocks 100a˜100c, a difference circuit 160, and a comparing circuit 176.
After a first reference voltage VREFP and a second reference voltage VREFN are received by the difference block 100c, a reference current Iref is outputted from a current output terminal Iout. The current output terminals Iout of the difference blocks 100a and 100b are connected with each other to output an input current Iin.
Moreover, the difference circuit 160 comprises a first part 162 and a second part 164. According to the relationship between the input current Iin and the reference current Iref, a V+ voltage of the second part 164 is correspondingly changed by the first part 162. For example, if the input current Iin is lower than the reference current Iref, the V+ voltage decreases and the V+ voltage is lower than the V− voltage. Whereas, if the input current Iin is higher than the reference current Iref, the V+ voltage increases and the V+ voltage is higher than the V− voltage.
For example, if the maximum values of the first input signal VP and the second input signal VM are lower than the first reference voltage VREFP and the minimum values of the first input signal VP and the second input signal VM are higher than the second reference voltage VREFN, the input current Iin is lower than the reference current Iref. Consequently, the V+ voltage is lower than the V− voltage. Under this circumstance, a detected signal VOUT issued from the comparing circuit 176 is in a first logic-level state (e.g. a high logic-level state). The detected signal VOUT in the first logic-level state represents the invalid differential input signal.
On the other hand, if the maximum values of the first input signal VP and the second input signal VM are higher than the first reference voltage VREFP and the minimum values of the first input signal VP and the second input signal VM are lower than the second reference voltage VREFN, the input current Iin is higher than the reference current Iref. Consequently, the V+ voltage increases and the V+ voltage is higher than the V− voltage. Under this circumstance, a detected signal VOUT issued from the comparing circuit 176 is in a second logic-level state (e.g. a low logic-level state). The detected signal VOUT in the second logic-level state represents the valid differential input signal.
FIG. 3A to FIG. 3C schematically illustrate the architecture of another conventional squelch detector. This squelch detector is disclosed in US Publication No. 2007/023849. As shown in FIG. 3A, the squelch detector 200 includes a differential offset biasing amplifier 210, a differential self-mixer 220 coupled to the differential offset biasing amplifier 210, a differential comparator 240, and a differential gain stage 230 coupled between the differential self-mixer 220 and the differential comparator 240.
The differential offset biasing amplifier 210 receives a differential input signal Vi=(Vi+−Vi−) at a first set of differential input terminals and a differential squelch detection threshold signal Vth=(Vth+−Vth−) at a second set of differential input terminals. The differential offset biasing amplifier 210 includes a first differential circuit 212 and a second differential circuit 214. In operation, the first differential circuit 212 subtracts the differential squelch detection threshold signal (Vth+−Vth−) from the differential input signal (Vi+−Vi−) to generate a first differential offset biased signal (V1a). The second differential circuit 214 adds the differential squelch detection threshold signal (Vth+−Vth−) to the differential input signal (Vi+−Vi−) to generate a second differential offset biased signal (V1b). Each differential circuit 212, 214 may also provide gain G as an integral function or the gain may be provided by a separate gain circuit 216, 218. Thereafter, the differential offset biased signals (V1a, V1b), are output by the differential offset biasing amplifier 210.
The differential self-mixer 220 receives the differential offset biased signals (V1a, V1b) at its input terminals. The differential self-mixer 220 is fully differential and selectively passes and mixes the detected positive and negative peaks from the differential offset biased signals and down converts the signal directly to a differential direct current signal (V2). Thereafter, the differential direct current signal (V2) is output by the differential self-mixer 220.
The differential gain stage 230 in this example is utilized to further amplify the differential direct current signal (V2) output by the differential self-mixer 220, when increased signal amplitude is desired by the application. The differential gain stage 230 amplifies the differential direct current signal (V2) by the gain K. Thereafter, the amplified differential direct current signal (V3) is output by the differential gain stage 230.
The differential comparator 240 receives the amplified differential direct current signal (V3) at its differential input. The differential comparator 240 converts the amplified differential direct current signal (V3) to a digital squelch signal (Vo). For example, when the potential of the amplified differential direct current signal (V3) is greater than zero, the differential comparator outputs a squelch signal (Vo) having a first logic level. When the potential of the differential direct current signal (V3) is substantially zero, the differential comparator outputs a squelch signal (Vo) having a second logic level. Thereafter, the squelch signal (Vo) is output by the differential comparator 240.
FIG. 3B shows an exemplary implementation of the differential offset biasing amplifier 210 of FIG. 3A. The differential offset biasing amplifier 210 includes a first transistor 241 and a second transistor 242 that are coupled to form a first differential pair. Likewise, the differential offset biasing amplifier 210 includes a third transistor 243 and fourth transistor 244 coupled to form a second differential pair. Further, the differential offset biasing amplifier 210 also includes a fifth transistor 245 and sixth transistor 246 coupled to form a third differential pair, and a seventh transistor 247 and eighth transistor 248 coupled to form a fourth differential pair.
Furthermore, the loads 249, 250, 251, 252 of the differential pairs may be resistive elements, inductive elements, transistors configured as active loads, or the like.
In operation, the first differential pair 241, 242 receives the differential input signal (Vi+−Vi−) at its input terminals and the third differential pair 245, 246 receives the differential squelch detection threshold signal (Vth+−Vth−) at its input terminals. The outputs of the first differential pair 241, 242 and third differential pair 245, 246 are coupled together such that the differential squelch detection threshold signal (Vth+−Vth−) is subtracted from the differential input signals (Vi+−Vi−). Similarly, the second differential pair 243, 244 receives the differential input signal (Vi+−Vi−) at its input terminals and the fourth differential pair 247, 248 receives the differential squelch detection threshold signal (Vth+−Vth−) at its input terminals. The outputs of the second differential pair 243, 244 and fourth differential pair 247, 248 are coupled together such that the differential squelch detection threshold signal (Vth+−Vth−) is added to the differential input signals (Vi+−Vi−).
Thus, the coupled first differential pair 241, 242 and third differential pair 245, 246 provide positive peak detection by subtracting the differential squelch detection threshold signal (Vth+−Vth−) from the differential input signal (Vi+−Vi−). The coupled second differential pair 243, 244 and fourth differential pair 247, 248 provide negative peak detection by adding the differential squelch detection threshold signal (Vth+−Vth−) to the differential input signal (Vi+−Vi−).
FIG. 3C shows an exemplary implementation of the differential self-mixer 220 of FIG. 3A. The differential self-mixer 220 includes first and second transistors 253, 254 coupled to form a first differential pair, and third and fourth transistors 255, 256 coupled to form a second differential pair. The differential self-mixer 220 also includes fifth and sixth transistors 257, 258 coupled to form a third differential pair, and seventh and eighth transistors 259, 260 coupled to form a fourth differential pair.
The first differential pair 253, 254 receives the first differential offset biased signal (V1a+, V1a−) and the second differential pair 255, 256 receives the second offset biased differential signal (V1b+, V1b−). The third differential pair 257, 258 is coupled in series with the first differential pair 253, 254. The fourth differential pair 259, 260 is coupled in series with the second differential pair 255, 256. The outputs of the first differential pair 253, 254 and second differential pair 255, 256 are coupled together such that the positive and negative peaks from the differential offset biased signals (V1a, V1b), that correspond to when the potential difference of the input signal (Vi) exceeds the potential difference of the squelch detection threshold signal (Vth), are selectively passed, mixed and down converted directly to a direct current signal (V2).
In particular, the third differential pair 257, 258 selectively provides the bias current IB to the first differential pair 253, 254 when the first side of the second differential offset biased signal (V1b+) is greater than the second side of the first differential offset biased signal (V1a−). Thus, the relatively small peaks of V1a 310 are selectively passed to the output during the relatively large peaks of V1b 330. Similarly, the fourth differential pair 259, 260 selectively provides the bias current IB to the second differential pair 255, 256 when the second side of the second differential offset biased signal (V1b−) is greater than the first side of the first differential offset biases signal (V1a+). Likewise, the relatively small peaks 320 of V1b are selectively passed to the output during the relatively large peaks 340 of V1a. 
The differential self-mixer 220 advantageously improves the dynamic range of the squelch detection signal, as compared to conventional squelch detectors. The direct conversion of the detected peaks to direct current also allows implementation of high gain amplifying using a single gain stage with low bias current in the differential gain stage 230, resulting in a reduction in power consumption and layout area in devices. signal VM are higher than the first reference voltage VREFP and the minimum values of the first input signal VP and the second input signal VM are lower than the second reference voltage VREFN, the input current Iin is higher than the reference current Iref. Consequently, the V+ voltage increases and the V+ voltage is higher than the V− voltage. Under this circumstance, a detected signal VOUT issued from the comparing circuit 176 is in a second logic-level state (e.g. a low logic-level state). The detected signal VOUT in the second logic-level state represents the valid differential input signal.